1. Field of the Invention
The present invention relates to a method for forming a field oxide film. More particularly, the present invention relates to a method for forming a field oxide film that can be aptly used in a flash memory having a floating gate.
2. Description of the Related Arts
A conventional flash memory having a floating gate will be hereinafter explained in conjunction with the attached drawings. FIG. 1 is a plan view of a flash memory, in which an active region 20 is defined on a silicon substrate 11 by a device isolation region formed of a LOCOS oxide film 17. A floating gate 13 is formed via a gate insulating film on the active region 20. A control gate 19 is formed over the floating gate 13 via an ONO film and extends from the LOCOS oxide film 17 to the active region 20. Also, source/drain regions 21a, 21b are formed in the active region 20 on both sides of the floating gate 13 and the control gate 19.
A method for manufacturing the above conventional flash memory will be hereinafter explained. Figures (a) each represent a view showing a cross section along the line X--X of FIG. 1, and Figures (b) each represent a view showing a cross section along the line Y--Y of FIG. 1. First, a gate insulating film 32 is formed to a thickness of about 100 .ANG. on a surface of a p-type silicon substrate 31, and then a polysilicon layer 33a for a floating gate is formed to a thickness of 1000 .ANG., as shown in FIGS. 18(a) and 18(b). Further, impurity ions are implanted into the polysilicon layer 33a by ion implantation (N.sup.+ :.sup.31 P.sup.+, 30 keV, 2.times.10.sup.15 /cm.sup.2). Subsequently, a lower oxide film 34 of a thickness of 100 .ANG. and a silicon nitride film 35 (hereafter referred to as a nitride film) of a thickness of 200 .ANG. are formed. The lower oxide film 34 and the nitride film 35 will be part of an ONO film HTO (High Temperature CVD Silicon Dioxide) 150 .ANG./SiN 250 .ANG./HTO 100 .ANG.! formed on the polysilicon layer 33a.
Then, a resist pattern 36 is formed on the nitride film 35 to cover the entire surface of the active region on the silicon substrate 31. With the resist pattern 36 used as a mask, the nitride film 35, the lower oxide film 34, the polysilicon layer 33a, and the gate insulating film 32 are successively etched, as shown in FIGS. 19(a) and 19(b).
Subsequently, the resist pattern 36 is removed and, with the nitride film 35 used as a mask, selective LOCOS oxidation is performed on the p-type silicon substrate 31 to form a field oxide film 37 to a thickness of 6000 .ANG. for device isolation of the active region, as shown in FIGS. 20(a) and 20(b). At this step, an oxide film of a thickness of about 100 .ANG. is formed on the nitride film 35. The oxide film will be an upper oxide film 38 of the ONO film. Also, at this step, an oxide film 39 is formed on the sidewall of the polysilicon layer 33a.
Next, a polysilicon layer 40a for a control gate is deposited to a thickness of 1000 .ANG., as shown in FIGS. 21(a) and 21(b), and ion implantation (N.sup.+ : .sup.31 P.sup.+, 60 keV, 5.times.10.sup.12 /cm.sup.2) is carried out into the polysilicon layer 40a.
Further, the polysilicon layer 40a, the upper oxide film 38, the nitride film 35, the lower oxide film 34, the polysilicon layer 33a, and the gate insulating film 32 are successively etched for forming the floating gate 33 and the control gate 40 with the resist pattern for forming the control gate 40 used as a mask, as shown in FIGS. 22(a) and 22(b).
Afterwards, source/drain regions (not shown) of a cell array region of the flash memory are formed by ion implantation (N.sup.+ : .sup.75 As.sup.+, 20 keV, 2.times.10.sup.15 /cm.sup.2). Further, NSG of a thickness of 1000 .ANG. and BPSG of a thickness of 5000 .ANG. are deposited by CVD method as an interlayer insulating film (not shown), followed by performing a melt processing at 900.degree. C. for 10 minutes, forming a contact hole by photoetching, depositing Al-Si-Cu to a thickness of 5000 .ANG. by a sputtering method, and forming a metal wiring (not shown) by photoetching to complete the flash memory.
Here, in order to prevent oxidation of the sidewall of the polysilicon layer 33a in the above method, a nitride film is further deposited on the nitride film 35 before performing the LOCOS oxidation of FIG. 20, followed by etching back to form a sidewall spacer 50 on the sidewall of the nitride film 35, the lower oxide film 34 and the polysilicon layer 33a, as shown in FIGS. 23(a) and 23(b). Here, the gate insulating film 32 is used as an etching stopper at the time of forming the sidewall spacer 50.
The above conventional manufacturing method forms, for example, two regions on the substrate; one region including only the polysilicon layer 40a for the control gate having a thickness of about 1000 .ANG., and the other region including a laminated film formed of the polysilicon layer 33a for the floating gate having a thickness of about 1000 .ANG., the ONO film (34, 35, 38) and the polysilicon layer 40a for the control gate, as shown in FIG. 22. This gives rise to a step difference of more than about 1000 .ANG. between the two regions. Therefore, in patterning the control gate, it is necessary to ensure the thickness of the field oxide film 37 under and near the end of the floating gate to be about 1000 .ANG. as an etching margin at the time of simultaneous etching of the polysilicon layer 33a for the floating gate, ONO film (34,35,38) and the polysilicon layer 40a for the control gate. In other words, if a sufficient etching margin is not ensured, the field oxide film 37 will be etched off at the time of simultaneous etching of the polysilicon layer 33a for the floating gate, ONO film (34,35,38) and the polysilicon layer 40a for the control gate and, further, the underlying silicon substrate 31 itself will be etched. This causes impurity ions to be implanted into the silicon substrate 31 where the field oxide film 37 is etched at a later step of implanting the impurity ions for forming the source/drain regions, making the device isolation impossible or the breakdown voltage lowered.
However, if a thin field oxide film is to be formed in accordance with microminiaturization, the field oxide thickness at the edge of the floating gate pattern becomes less than enough for simultaneous etching of the polysilicon layer 33a for the floating gate, the ONO film and the polysilicon layer 40a for the control gate. For example, if a field oxide film of about 3000 .ANG. is formed, the reach (A) of the bird's beak into the active region under the floating gate will be as small as about 500 .ANG., and the thickness (B in FIG. 24) of the field oxide film 37 under the end of the floating gate will be smaller than about 1000 .ANG..
Therefore, it is necessary to form a thick field oxide film 37 of about 6000 .ANG. in order to ensure the thickness (B) of the etching margin to be about 1000 .ANG. which corresponds to the step difference of the polysilicon layers or the like. If the filed oxide film 37 is formed to a thickness of about 6000 .ANG., the reach of the bird's beak of the field oxide film under the floating gate will be as large as about 1500 .ANG.. This reduces the area of the active region. However, the wider area is necessary to obtain enough active region, so that the area occupied by the semiconductor memory device itself must inevitably be increased.
Here, it is possible to reduce the reach of the bird's beak by a sidewall spacer 50, as shown in FIG. 23. However, even in this case, the thickness (B) of the field oxide film 37 under the end of the floating gate is approximately the same as the above, causing a similar problem.
As mentioned earlier, recent semiconductor memory devices are oriented towards reduction of the driving voltages, thinning of the field oxide film, and reduction of the step difference caused by the field oxide film in accordance with the development of the microminiaturization technique. However, in view of protecting the substrate, it is difficult to achieve a sufficiently thin field oxide film, as described above.